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DS1330Y/ab 256k nonvolatile sram with battery monitor DS1330Y/ab 042398 1/11 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? power supply monitor resets processor when v cc power loss occurs and holds processor in reset during v cc rampup ? battery monitor checks remaining capacity daily ? read and write access times as fast as 70 ns ? unlimited write cycle endurance ? typical standby current 50 m a ? upgrade for 32k x 8 sram, eeprom or flash ? lithium battery is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (DS1330Y) or optional 5% v cc operating range (ds1330ab) ? optional industrial temperature range of 40 c to +85 c, designated ind ? new powercap module (pcm) package directly surfacemountable module replaceable snapon powercap provides lith- ium backup battery standardized pinout for all nonvolatile sram products detachment feature on powercap allows easy removal using a regular screwdriver pin assignment bw oe ce we rst v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 34 33 32 31 30 29 28 27 26 25 24 23 22 14 15 16 17 21 20 19 18 nc nc a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 nc nc dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 34pin powercap module (pcm) gnd v bat (uses ds9034pc powercap) pin description a0a14 address inputs dq0dq7 data in/data out ce chip enable we write enable oe output enable rst reset output bw battery warning output v cc power (+5 volts) gnd ground nc no connect description the ds1330 256k nonvolatile srams are 262,144bit, fully static, nonvolatile srams organized as 32,768 words by eight bits. each nv sram has a selfcon- tained lithium energy source and control circuitry which constantly monitors v cc for an outoftolerance condi- tion. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. additionally, the ds1330 devices have dedicated cir- cuitry for monitoring the status of v cc and the status of the internal lithium battery. ds1330 devices in the pow- ercap module package are directly surface mountable and are normally paired with a ds9034pc powercap to form a complete nonvolatile sram module. the devices can be used in place of 32k x 8 sram, eeprom or flash components.
DS1330Y/ab 042398 2/11 read mode the ds1330 devices execute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 15 address inputs (a 0 a 14 ) defines which of the 32,768 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later occurring signal (ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1330 devices excute a write cycle whenever the we and ce signals are in the active (low) state after address inputs are stable. the later occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus con- tention. however, if the output drivers are enabled (ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1330ab provides full functional capability for v cc greater than 4.75 volts and write protects by 4.5 volts. the DS1330Y provides full functional capability for v cc greater than 4.5 volts and write protects by 4.25 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply volt- age decay, the nv srams automatically write protect themselves, all inputs become adon't care,o and all out- puts become high impedance. as v cc falls below approximately 2.7 volts, the power switching circuit con- nects the lithium energy source to ram to retain data. during powerup, when v cc rises above approximately 2.7 volts, the power switching circuit connects external v cc to the ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1330ab and 4.5 volts for the DS1330Y. system power monitoring ds1330 devices have the ability to monitor the external v cc power supply. when an outoftolerance power supply condition is detected, the nv srams warn a pro- cessorbased system of impending power failure by asserting rst . on power up, rst is held active for 200 ms nominal to prevent system operation during pow- eron transients and to allow t rec to elapse. rst has an opendrain output driver. battery monitoring the ds1330 devices automatically perform periodic battery voltage monitoring on a 24 hour time interval. such monitoring begins within t rec after v cc rises above v tp and is suspended when power failure occurs. after each 24 hour period has elapsed, the battery is connected to an internal 1 m w test resistor for one second. during this one second, if battery voltage falls below the battery voltage trip point (2.6v), the battery warning output bw is asserted. once asserted, bw remains active until the module is replaced. the battery is still retested after each v cc powerup, however, even if bw is active. if the battery voltage is found to be higher than 2.6v during such testing, bw is deasserted and regular 24hour testing resumes. bw has an open drain output driver. freshness seal each ds1330 is shipped from dallas semiconductor with its lithium energy source disconnected, guarantee- ing full energy capacity. when v cc is first applied at a level greater than v tp , the lithium energy source is enabled for battery backup operation. packages the 34pin powercap module integrates sram memory and nonvolatile control along with contacts for connection to the lithium battery in the ds9034pc pow- ercap. the powercap module package design allows a ds1330 pcm device to be surface mounted without subjecting its lithium backup battery to destructive high temperature reflow soldering. after a ds1330 pcm is reflow soldered, a ds9034pc is snapped on top of the pcm to form a complete nonvolatile sram module. the ds9034pc is keyed to prevent improper attach- ment. ds1330 powercap modules and ds9034pc powercaps are ordered separately and shipped in sep- arate containers. see the ds9034pc data sheet for fur- ther information.
DS1330Y/ab 042398 3/11 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c, 40 c to +85 c for ind parts storage temperature 40 c to +70 c, 40 c to +85 c for ind parts soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes ds1330ab power supply voltage v cc 4.75 5.0 5.25 v DS1330Y power supply voltage v cc 4.5 5.0 5.5 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 0.8 v (v cc =5v 5% for ds1330ab) dc electrical characteristics (t a : see note 10) (v cc =5v 10% for DS1330Y) parameter symbol min typ max units notes input leakage current i il 1.0 +1.0 m a i/o leakage current ce v ih v cc i io 1.0 +1.0 m a output current @ 2.4v i oh 1.0 ma 14 output current @ 0.4v i ol 2.0 ma 14 standby current ce = 2.2v i ccs1 200 600 m a standby current ce = v cc 0.5v i ccs2 50 150 m a operating current i cco1 85 ma write protection voltage (ds1330ab) v tp 4.50 4.62 4.75 v write protection voltage (DS1330Y) v tp 4.25 4.37 4.5 v capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf
DS1330Y/ab 042398 4/11 (v cc =5v 5% for ds1330ab) ac electrical characteristics (t a : see note 10) (v cc =5v 10% for DS1330Y) parameter symbol ds1330ab70 DS1330Y70 ds1330ab100 DS1330Y100 units notes parameter symbol min max min max units notes read cycle time t rc 70 100 ns access time t acc 70 100 ns oe to output valid t oe 35 50 ns ce to output valid t co 70 100 ns oe or ce to output active t coe 5 5 ns 5 output high z from deselection t od 25 35 ns 5 output hold from address change t oh 5 5 ns write cycle time t wc 70 100 ns write pulse width t wp 55 75 ns 3 address setup time t aw 0 0 ns write recovery time t wr1 t wr2 5 12 5 12 ns 12 13 output high z from we t odw 25 35 ns 5 output active from we t oew 5 5 ns 5 data setup time t ds 30 40 ns 4 data hold time t dh1 t dh2 0 7 0 7 ns 12 13 read cycle t rc t acc v ih v il v ih v il v ih v il t oh v ih t od t od v ih v oh v ol v oh v ol t coe t coe output data valid d out oe addresses v ih v ih t oe v il v il ce t co see note 1
t wc v il v ih v il v ih v il v ih addresses ce we d out d in data in stable t aw t wp t wr2 v ih v il v il v il v ih v ih v il v il t coe t odw t ds t dh2 v il v ih v il v ih see notes 2, 3, 4, 6, 7, 8 and 13 DS1330Y/ab 042398 5/11 write cycle 1 t wc v ih v il v ih v il v ih v il addresses t aw data in stable high impedance v il v il v il v il v ih v ih t wp t wr1 t odw t oew t ds t dh1 v ih v il v ih v il ce we d out d in see notes 2, 3, 4, 6, 7, 8 and 12 write cycle 2
DS1330Y/ab 042398 6/11 powerdown/powerup condition v cc 2.7v t f t pd t r t rec backup current- supplied from lithium battery ce , we v tp t bpu t rpu t rpd rst bw v il v ih slews with v cc v il see notes 11 and 14 t dr slews with v cc t pu v ih battery warning detection battery t bpu v tp v bat test active bw t btc t bw t btpw v cc v il see note 14 2.6v
DS1330Y/ab 042398 7/11 powerdown/powerup timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 m s 11 v cc slew from v tp to 0v t f 150 m s v cc fail detect to rst active t rpd 15 m s 14 v cc slew from 0v to v tp t r 150 m s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms v cc valid to rst inactive t rpu 150 200 350 ms 14 v cc valid to bw valid t bpu 1 s 14 battery warning timing (t a : see note 10) parameter symbol min typ max units notes battery test cycle t btc 24 hr battery test pulse width t btpw 1 s battery test to bw active t bw 1 s (t a = 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period.
DS1330Y/ab 042398 8/11 9. each ds1330 has a builtin switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. all ac and dc electrical characteristics are valid over the full operating temperature range. for commercial prod- ucts, this range is 0 c to 70 c. for industrial products (ind), this range is 40 c to +85 c. 11. in a power down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. rst and bw are opendrain outputs and cannot source current. external pullup resistors should be connected to these pins for proper operation. both pins will sink 10 ma. dc test conditions outputs open cycle = 200 ns for operating current all voltages are referenced to ground ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns ordering information ds1330 ttp sss iii operating temperature range blank: 0 to 70 ind: 40 to +85 c access 70: 100: speed 70 ns 100 ns package type p: 34pin powercap module v cc tolerance ab: + 5% y: + 10%
DS1330Y/ab 042398 9/11 DS1330Y/ab nonvolatile sram, 34pin powercap module pkg dim inches min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 top view side view bottom view: reference only components and placements may differ from those shown
DS1330Y/ab 042398 10/11 DS1330Y/ab nonvolatile sram, 34pin powercap module with powercap pkg dim inches min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 top view side view bottom view: reference only components and placements may differ from those shown assembly and use reflow soldering dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented labelside up (livebug). hand soldering and touchup do not touch soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove part, apply flux, heat pad until solder reflows, and use a solder wick. lpm replacement in a socket to replace a low profile module in a 68pin plcc socket, attach a ds9034pc powercap to a module base then insert the complete module into the socket one row of leads at a time, push- ing only on the corners of the cap. never apply force to the center of the device. to remove from a socket, use a plcc extraction tool and ensure that it does not hit or damage any of the module ic components. do not use any other tool for extraction.
DS1330Y/ab 042398 11/11 recommended powercap module land pattern pkg dim inches min nom max a 1.050 b 0.826 c 0.050 d 0.030 e 0.112 a d b c e 16 pl recommended powercap module solder stencil pkg dim inches min nom max a 1.050 b 0.890 c 0.050 d 0.030 e 0.080 a d b c e 16 pl

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